The following patent is hereby incorporated by reference herein: U.S. Pat. No. 7,271,750 (“the '750 patent”), issued Sep. 18, 2007.
Pipelined analog-to-digital converters (“ADCs”) that are used for sampling often require specific signal-to-noise ratios or high sampling rates. These converters contain a plurality of stages, each of the stages having a multiplying DAC (“MDAC”) and a flash ADC, with the first few stages requiring large sampling capacitors and a large amplifier within the MDAC. FIG. 1 illustrates such an amplifier in one stage of the ADC. Amplifier 1 contains two stages, a cascode amplifier as the first stage, and a differential pair as the second stage. Amplifier 1 needs a high gain and a high bandwidth for proper operation of the MDAC. However, a high gain and a high bandwidth necessitate a high power consumption which is not desirable for the converter. Reducing the power consumption of the converter may be undertaken by relaxing the gain and bandwidth requirements of the amplifier within the MDAC. However, relaxing gain and bandwidth requirements creates inter-stage errors that are temperature and sample rate dependent.
The summing-node-sampling (“SNS”) calibration algorithm, discussed in the '750 patent, is an algorithm that allows for simultaneously lowering the open-loop gain and the bandwidth of the amplifier within the MDAC. This allows for the power consumption of the ADC to be lowered and the inter-stage gain errors can be corrected by the SNS algorithm. The SNS algorithm samples the voltage at the summing-node of the MDAC (“summing-node voltage”) and processes the samples at a sample rate that is lower than the sample rate of the converter, which significantly decreases the power consumption of the calibration engine. The summing-node voltage is amplified by a predetermined gain and then digitized using a separate analog-to-digital converter. The open-loop gain of residue amplifier 1 can be estimated from the output of the MDAC (“residue voltage”) and the summing-node voltage, and therefore the SNS algorithm assists in determining the amplifier's open-loop gain.
The digitized summing-node voltage and a separately digitized residue voltage are first high pass filtered to remove offset and then processed using a least-mean-square (“IMS”) algorithm to filter out noise and estimate the amplifier's open-loop gain. The LMS algorithm is used by the SNS algorithm and can correct the inter-stage gain error through a digital correction or through an analog correction.
Digitally correcting the inter-stage error can be done by using the LMS algorithm to iteratively estimate the value of the inverse of the gain α (where α=1/A, A being the open-loop gain of the amplifier). The estimate of α is done to find the value of α that minimizes the error, as shown in equation (i).
                              ɛ          =                                    [                                                α                  ⁢                                                                          ⁢                                      D                    ⁡                                          (                                              V                                                  o                          ⁢                                                                                                          ⁢                          1                                                                    )                                                                      -                                  D                  ⁡                                      (                                                                  V                                                  o                          ⁢                                                                                                          ⁢                          1                                                                    A                                        )                                                              ]                        2                          ,                            (        i        )            where ε is the algorithm estimation error squared, D(x) is the digital value of x, and Vo1 is the residue voltage of the first stage.
Equation (ii) may illustrate estimating an inverse of the open-loop gain of the amplifier iteratively, where:
                                          α                          i              +              1                                =                                    α              i                        -                          μ              ⁢                                                          ⁢                                                D                  ⁡                                      (                                          V                                              o                        ⁢                                                                                                  ⁢                        1                        ⁢                        i                                                              )                                                  ⁡                                  [                                                                                    α                        i                                            ⁢                                              D                        ⁡                                                  (                                                      V                                                          o                              ⁢                                                                                                                          ⁢                              1                              ⁢                              i                                                                                )                                                                                      -                                          D                      ⁡                                              (                                                                              V                                                          o                              ⁢                                                                                                                          ⁢                              1                              ⁢                              i                                                                                A                                                )                                                                              ]                                                                    ,                            (        ii        )            where α1 is the ith iteration of α and μ is the algorithm step size.
      (                  V                  o          ⁢                                          ⁢          1          ⁢          i                    A        )    ,
If Ve1 represents the summing-node voltage of the first stage of the ADC equation (ii) may be further shown by equation (iii):αi+1=αi−μD(Vo1i)[αiD(Vo1i)−D(Ve1)]  (iii).
An iterative determination of the inverse of the gain α which minimizes the error, allows for the digital correction of the gain error by multiplying the residue voltage by a correction factor. This may be represented by equation (iv):Vo1cor=Vo1(1+Kα)  (iv),where Vo1cor is the calibrated residue voltage of the first stage of the pipeline, and K is a correction factor that is the inverse of the feedback factor.
The LMS algorithm can also correct the inter-stage error through an analog correction. The analog correction can be done by using the LMS algorithm to maximize the open-loop gain of the amplifier A, by using a bias voltage gain (Vgain) derived in a positive-feedback circuit connected to the amplifier. Vgain is depicted in FIG. 1. A maximum value of an open-loop gain can thus be enabled regardless of changes in temperature, supply, and process. A positive-feedback circuit 2 can be connected across the internal nodes of the amplifier 1. FIG. 2 further illustrates the positive-feedback circuit 2 connected to the internal nodes of residue amplifier 1. The feedback circuit 2 creates a negative transconductance circuit in parallel with the output impedance of the first stage of the amplifier. This negative transconductance reduces the output conductance of the first stage of the amplifier shown in FIG. 1, thereby increasing the open-loop gain. This can be done by matching output impedance of the first stage of the amplifier with an opposite negative trans-impedance of the positive feedback circuit 2. Matching can be achieved by varying Vgain shown in FIGS. 1 and 2. Rather than providing an estimate for the inverse of the gain of α as done through digital correction, through analog correction, the LMS algorithm can minimize the estimate of a by controlling Vgain. This is illustrated in equation (v):
                                          V                          gain                              i                +                1                                              =                                    V                              gain                i                                      -                          μ              ⁢                                                          ⁢                              D                ⁡                                  (                                      V                                          o                      ⁢                                                                                          ⁢                      1                      ⁢                      i                                                        )                                            ⁢                              D                ⁡                                  (                                                            V                                              o                        ⁢                                                                                                  ⁢                        1                        ⁢                        i                                                              A                                    )                                                                    ,                            (        v        )            where Vgaini is ith iteration of the bias voltage gain from the feedback circuit.
      (                  V                  o          ⁢                                          ⁢          1          ⁢          i                    A        )    ,
As Ve1 represents the summing-node voltage of the first stage of the pipeline equation (v) may be rewritten by equation (vi):Vgaini+1=Vgaini−μD(Vo1i)D(Ve1)  (vi).
Although the LMS algorithm attempts to filter noise and perturbations from the digitized summing-node voltage and the residue voltage, the algorithm as discussed in the '750 patent is insufficient to filter perturbations correlated with these signals whether digital or analog correction is undertaken. A measurement of the summing-node voltage may be affected by the input signal due to coupling, as sampling occurs continuously and all of the samples are used by the algorithm. Noise and perturbations accompany the sampled summing-node voltage and the residue signals, and can be correlated with the summing-node voltage and the residue voltage. Therefore, the noise and perturbations may not be not sufficiently filtered by the LMS algorithm. These perturbations can greatly alter a convergence or an estimation of the open-loop gain (or inverse of the gain) or if the error is corrected through analog calibration, the convergence of the bias voltage.
Thus there remains a need in the art, for a modified algorithm which may allow for the removal of unwanted perturbations and noise associated with the summing-node voltage and the residue voltage signals.